The invention relates to error detection and correction.
Error correction codes (ECCs) have been developed that both detect and correct certain errors. One well known class of ECC algorithm is the "Hamming codes," which are widely used in digital communications data storage systems. The Hamming codes are capable of detecting multiple bit errors and correcting single bit errors. A detailed description of the Hamming codes is found in Shu Lin et al., "Error Control Coding, Fundamentals and Applications," Chapter 3 (1982). Another well known ECC algorithm is the "Reed-Solomon code" widely used for error correction in the compact disk industry. A detailed description of this ECC algorithm is found in Hoeve et al., "Error Correction and Concealment in the Compact Disk System," Philips Technical Review, Vol. 40, No. 6, pp. 166-172 (1980). The Reed-Solomon code is able to correct two errors per word. Other conventional ECC algorithms include the b-adjacent error correction code described in D. C. Bossen, "B-Adjacent Error Correction," IBM J. Res. Develop., pp. 402-408 (July 1970), and the odd weight column codes described in M. Y. Hsiao, "A Class of Optimal Minimal Odd Weight Column SEC-DED Codes," IBM J. Res. Develop., pp. 395-400 (July 1970). The Hsiao codes, like the Hamming codes, are capable of detecting double-bit errors and correcting single-bit errors. The Hsiao codes use the same number of check bits as the Hamming codes (e.g., 8 check bits for 64 bits of data), but are superior in that hardware implementation is simplified and speed of error detection is improved.
Another type of ECC algorithm, which has been used in computer memory sub-systems, is described in co-pending and commonly assigned U.S. patent application Ser. No. 07/955,923, filed Oct. 2, 1992, entitled "Error Correction System for N Bits Using Error Correction Designed for Fewer than N Bits." The ECC algorithm described in this prior application, when coupled with a particular data distribution architecture, obtains the advantages of the Hamming codes with the same overhead (8 check bits for 64 bits of data), but also is able to correct any single 4-bit wide error.
Other types of ECC algorithms are described in co-pending and commonly assigned U.S. patent application Ser. No. 08/599,757, filed Feb. 12, 1996, entitled "Error Correction Codes"; and U.S. patent application Ser. No. 08/658,732, filed Jun. 5, 1996, entitled "Data Error Detection and Correction." The '757 application discusses using check bits to perform error detection and correction of both memory address and data signals.
Referring to FIG. 9, the Pentium.RTM. Pro processor chip set (from Intel Corporation), commonly referred to as the Orion chip set in the computer industry, contains the Pentium.RTM. Pro processor 300 connected to a processor bus 301 and a memory subsystem 310, which includes control and address block 302 and a data buffers block 306. The memory subsystem includes ECC logic in data buffers 306 for performing error detection and correction of memory data on memory data bus 303. Eight ECC bits on the memory data bus 303, which protect the memory data bus in the Orion chip set, are capable of correcting single-bit errors, detecting double-bit errors, and detecting all errors confined to one nibble on the memory data bus.
The Pentium.RTM. Pro processor bus 301 also includes eight processor ECC bits for detecting and correcting errors in the data lines of the processor bus. The Pentium.RTM. Pro processor bus 301 also includes parity protection for address/request signals and most control signals. A two-bit parity code protects the address portion of the processor bus. A first parity bit, represented as AP[0].sub.--, protects processor address bits A[23:3].sub.-- of the Pentium.RTM. Pro processor bus 301. A second address parity bit, represented as AP[1].sub.--, protects processor address bits A[31:24].sub.-- and A[35:24].sub.--. Other parity bits are used to protect control signals on the Pentium.RTM. Pro processor bus 301.